Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 255 of 584
REJ09B0240-0150
13.5.2 Output Compare Output Timing
The compare match signal is generated in the last state in which TRCCNT and GR match (when
TRCCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TRCIOR is output on the compare match output pin
(FTIOA, FTIOB, FTIOC, or FTIOD).
When TRCCNT matches GR, the compare match signal is generated only after the next counter
clock pulse is input.
Figure 13.25 shows the output compare timing.
GRA to GRD
TRCCNT
TCNT input
clock
φ
N
N
N + 1
Compare
match signal
FTIOA to FTIOD
Figure 13.25 Output Compare Output Timing