Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 256 of 584
REJ09B0240-0150
13.5.3 Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TRCIOR0 and TRCIOR1. Figure 13.26 shows the timing when the falling edge is selected.
TRCCNT
Input capture
input
φ
N – 1 N N + 1 N + 2
N
GRA to GRD
Input capture
signal
Figure 13.26 Input Capture Input Signal Timing
13.5.4 Timing of Counter Clearing by Compare Match
Figure 13.27 shows the timing when the counter is cleared by compare match A. When the GRA
value is N, the counter counts from 0 to N, and its cycle is N + 1.
TRCCNT
Compare
match signal
φ
GRA
N
N H'0000
Figure 13.27 Timing of Counter Clearing by Compare Match