Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 258 of 584
REJ09B0240-0150
13.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TRCCNT matches the general
register.
The compare match signal is generated in the last state in which the values match (when TRCCNT
is updated from the matching count to the next count). Therefore, when TRCCNT matches a
general register, the compare match signal is generated only after the next TRCCNT clock pulse is
input.
Figure 13.30 shows the timing of the IMFA to IMFD flag setting at compare match.
GRA to GRD
TRCCNT
TRCCNT input
clock
φ
N
N
N + 1
Compare
match signal
IMFA to IMFD
IRRTRC
Figure 13.30 Timing of IMFA to IMFD Flag Setting at Compare Match