Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 259 of 584
REJ09B0240-0150
13.5.7 Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure
13.31 shows the timing of the IMFA to IMFD flag setting at input capture.
GRA to GRD
TRCCNT
Input
capture
signal
φ
N
N
IMFA to IMFD
IRRTRC
Figure 13.31 Timing of IMFA to IMFD Flag Setting at Input Capture