Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 260 of 584
REJ09B0240-0150
13.5.8 Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 13.32 shows the status flag clearing timing.
IMFA to IMFD
Write signal
Address
φ
TRCSR address
IRRTRC
TRCSR
write cycle
T1 T2 T3 T4
Figure 13.32 Timing of Status Flag Clearing by CPU