Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 261 of 584
REJ09B0240-0150
13.6 Usage Notes
The following types of contention or operation can occur in timer RC operation.
1. The pulse width of the input clock signal and the input capture signal must be at least three
system clock (φ) cycles when the CKS2 to CKS0 bits in TRCCR1 = B'0XX or B'10X, and at
least three on-chip oscillator clock (φ40M) cycles for B'110; shorter pulses will not be detected
correctly.
2. Writing to registers is performed in the T4 state of a TRCCNT write cycle.
If counter clear signal occurs in the T4 state of a TRCCNT write cycle, clearing of the counter
takes priority and the write is not performed, as shown in figure 13.33. If counting-up is
generated in the TRCCNT write cycle to contend with the TRCCNT counting-up, writing
takes precedence.
3. TRCCNT may erroneously count up when switching internal clocks. TRCCNT counts the
rising edge of the divided system clock (φ) when the internal clock is selected. If clocks are
switched as shown in figure 13.34, the change from the low level of the previous clock to the
high level of the new clock is considered as the rising edge. In this case, TRCCNT counts up
erroneously.
4. If timer RC enters the module standby mode while an interrupt is being requested, the interrupt
request cannot be cleared. Before entering the module standby mode, disable interrupt
requests.
Counter clear
signal
Write signal
Address
φ
TCNT address
TRCCNT
TRCCNT write cycle
T1
T2
N H'0000
T3 T4
Figure 13.33 Contention between TRCCNT Write and Clear