Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 262 of 584
REJ09B0240-0150
TRCCNT
Previous clock
N
N + 1 N + 2 N + 3
New clock
Counter clock
Erroneous rising edge may occur depending on the timing
of changing bits CKS2 to CKS0. In this case, TRCCNT
counts up.
Figure 13.34 Internal Clock Switching and TRCCNT Operation
5. The TOA to TOD bits in TRCCR1 decide the value of the FTIO pin, which is output until the
first compare match occurs. Once a compare match occurs and this compare match changes the
values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the
values read from the TOA to TOD bits may differ. Moreover, when the writing to TRCCR1
and the generation of the compare match A to D occur at the same timing, the writing to
TRCCR1 has the priority. Thus, output change due to the compare match is not reflected to the
FTIOA to FTIOD pins. Therefore, when bit manipulation instruction is used to write to
TRCCR1, the values of the FTIOA to FTIOD pin output may result in an unexpected result.
When TRCCR1 is to be written to while compare match is operating, stop the counter once
before accessing to TRCCR1, read the port 8 state to reflect the values of FTIOA to FTIOD
output, to TOA to TOD, and then restart the counter. Figure 13.35 shows an example when the
compare match and the bit manipulation instruction to TRCCR1 occur at the same timing.