Datasheet

Section 13 Timer RC
Rev. 1.50 Sep. 18, 2007 Page 263 of 584
REJ09B0240-0150
Compare match B
signal
φ
FTIOB pin
TRCCR1
write signal
Setting
Bit
TRCCR1
0
CCLR
0
CKS2
0
CKS1
0
CKS0
0
TOD
1
TOC
1
TOB
0
765 43210
TOA
Expected
output
Remains high because the writing 1 to TOB has priority
TRCCR1 has been set to H'06. Compare match B and compare match C are used. The FTIOB pin output 1,
and is set to the toggle output or the 0 output on compare match B.
When the TOC bit is cleared (the FTIOC signal is low) by execution of BCLR #2,@TRCCR1 and compare
match B occurs at the same timing as shown below, writing H'02 to TRCCR has priority and the FTIOB
signal is not driven low on compare match B; the FTIOB signal remains high.
BCLR #2,@TRCCR1
(1) TRCCR1 is read as H'06.
(2) TRCCR1 is modified from H'06 to H'02.
(3) H'02 is written to TRCCR1.
Figure 13.35 When Compare Match and Bit Manipulation Instruction to TRCCR1
Occur at the Same Timing