Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 265 of 584
REJ09B0240-0150
Section 14 Timer RD
This LSI has two units of 16-bit timers (timer RD_0 and timer RD_1), each of which has two
channels. Table 14.1 lists the timer RD functions, table 14.2 lists the channel configuration of
timer RD, and figure 14.1 is a block diagram of the entire timer RD. Block diagrams of channels 1
and 2 are shown in figures 14.2 and 14.3.
Timer RD_1 has the same functions as timer RD_0. Therefore, the unit number (_0 or _1) is not
explicitly mentioned in this section unless otherwise noted.
14.1 Features
• Capability to process up to eight inputs/outputs 0
• Eight general registers (GR): four registers for each channel
 Independently assignable output compare or input capture functions
• Selection of seven counter clock sources: six internal clocks (φ, φ/2, φ/4, φ/8, φ/32, and φ40M
which is a 40-MHz/32-MHz clock derived from the on-chip oscillator) and an external clock
• Seven selectable operating modes
 Timer mode
Output compare function (Selection of 0 output, 1 output, or toggle output)
Input capture function (Rising edge, falling edge, or both edges)
 Synchronous operation
Timer counters_0 and _1 (TRDCNT_0 and TRDCNT_1) can be written simultaneously.
Simultaneous clearing by compare match or input capture is possible.
 PWM mode
Up to six-phase PWM output can be provided with desired duty ratio.
 PWM3 mode
One-phase PWM output for non-overlapped normal and counter phases
 Reset synchronous PWM mode
Three-phase PWM output for normal and counter phases
 Complementary PWM mode
Three-phase PWM output for non-overlapped normal and counter phases
The A/D conversion start trigger can be set for PWM cycles.
 Buffer operation
The input capture register can be consisted of double buffers.
The output compare register can automatically be modified.