Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 266 of 584
REJ09B0240-0150
• High-speed access by the internal 16-bit bus
 16-bit TRDCNT and GR registers can be accessed in high speed by a 16-bit bus interface
• Any initial timer output value can be set
• Output of the timer is disabled by external trigger
• Eleven interrupt sources
 Four compare match/input capture interrupts and an overflow interrupt are available for
each channel. An underflow interrupt can be set for channel 1.