Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 269 of 584
REJ09B0240-0150
ITMRD0
FTIOA0
ITMRD1
ADTRG
Channel 0
timer
Channel 1
timer
Module data bus
FTIOB0
FTIOC0
FTIOD0
FTIOA1
FTIOB1
FTIOC1
FTIOD1
TRDSTR:
TRDMDR:
TRDPMR:
TRDFCR:
TRDOER1:
TRDOER2:
TRDOCR:
ADTRG:
ITMRD0:
ITMRD1:
[Legend]
Timer RD start register (8 bits)
Timer RD mode register (8 bits)
Timer RD PWM mode register (8 bits)
Timer RD function control register (8 bits)
Timer RD output master enable register 1 (8 bits)
Timer RD output master enable register 2 (8 bits)
Timer RD output control register (8 bits)
A/D conversion start trigger output signal
Channel 0 interrupt
Channel 1 interrupt
Control logic
φ, φ/2,
φ/4, φ/8,
φ/32, φ40M
TRDOI
TRDOER1
TRDOCR
TRDPMR TRDFCR
TRDSTR TRDMDR
TRDOER2
Figure 14.1 Timer RD Block Diagram