Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 274 of 584
REJ09B0240-0150
• Timer RD counter_1 (TRDCNT_1)
• General register A_1 (GRA_1)
• General register B_1 (GRB_1)
• General register C_1 (GRC_1)
• General register D_1 (GRD_1)
14.3.1 Timer RD Start Register (TRDSTR)
TRDSTR selects the operation/stop for the TRDCNT counter. Use a MOV instruction to modify
this register.
Bit Bit Name
Initial
Value R/W Description
7 to 4  All 1  Reserved
These bits are always read as 1, and cannot be
modified.
3 CSTPN1 1 R/W Channel 1 Counter Stop
0: Counting is stopped on a compare match of
TRDCNT_1 and GRA_1
1: Counting is continued on a compare match of
TRDCNT_1 and GRA_1
Set this bit to 1 to restart counting after the counting has
been stopped on a compare match.
2 CSTPN0 1 R/W Channel 0 Counter Stop
0: Counting is stopped on a compare match of
TRDCNT_0 and GRA_0
1: Counting is continued on a compare match of
TRDCNT_0 and GRA_0
Set this bit to 1 to restart counting after the counting has
been stopped on a compare match.