Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 276 of 584
REJ09B0240-0150
Figures 14.4 and 14.5 show examples of stopping operation of the counter in PWM3 mode, when
the CCLR2 to CCLR0 bits in TRDCR are set to clear TRDCNT_0 on GRA_0 compare match. For
details on PWM3 mode, refer to section 14.4.8, PWM3 Mode Operation.
The value of TRDCNT
Set to 1 by writing from the CPU
Cleared to 0 by GRA_0 compare match
H'FFFF
H'0000
GRA_0
GRA_1
GRB_0
GRB_1
FTIOA0
FTIOB0
STR0
CSTPN0
Counter cleared by GRA_0 compare match
Time
Figure 14.4 Example (1) of Stopping Operation of the Counter (in PWM3 Mode)
The value of TRDCNT
Counter cleared by GRA_0 compare match
H'FFFF
H'0000
GRA_0
GRA_1
GRB_0
GRB_1
FTIOA0
FTIOB0
STR0
CSTPN0
High
Time
Set to 1 by writing from the CPU Cleared to 0 by writing from the CPU
Figure 14.5 Example (2) of Stopping Operation of the Counter (in PWM3 Mode)