Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 277 of 584
REJ09B0240-0150
Figure 14.6 shows an example of starting and stopping operations of counters in PWM3 mode,
when TRDCNT_0 is set to be cleared and stopped on GRA_0 compare match (CCLR2 to CCLR0
= 001, CSTPNT0 = 0) and TRDCNT_1 is used as a free-running counter. When TRDCNT_1
starts counting by setting the STR1 bit to 1 after TRDCNT_0 has started counting by setting the
STR0 bit to 1, set 0 in the STR0 bit and 1 in the STR1 bit by using a MOV instruction. If the bit
manipulation instruction is used to set 1 in the STR1 bit, there is a possibility that the STR0 bit is
set to 1 after the counting has stopped on GRA_0 compare match, and that TRDCNT_0 starts
counting again.
The value of TRDCNT
0 is written in STR0, 1 in STR1, 0 in CSTPN0,
and 1 in CSTPN1 by the CPU
0 written in STR0 by the CPU
is not reflected
H'FFFF
H'0000
GRA_0
GRA_1
GRB_0
GRB_1
FTIOA0
FTIOB0
STR1
STR0
CSTPN1
TRDCNT_0
TRDCNT_1
High
CSTPN0
Low
Counter cleared by GRA_0
compare match
Time
Figure 14.6 Example of Starting and Stopping Operations of Counters (in PWM3 Mode)