Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 278 of 584
REJ09B0240-0150
14.3.2 Timer RD Mode Register (TRDMDR)
TRDMDR selects buffer operation settings and synchronized operation.
Bit Bit Name
Initial
Value R/W Description
7 BFD1 0 R/W Buffer Operation D1
0: GRD_1 operates normally
1: GRB_1 and GRD_1 are used together for buffer
operation
6 BFC1 0 R/W Buffer Operation C1
0: GRC_1 operates normally
1: GRA_1 and GRD_1 are used together for buffer
operation
5 BFD0 0 R/W Buffer Operation D0
0: GRD_0 operates normally
1: GRB_0 and GRD_0 are used together for buffer
operation
4 BFC0 0 R/W Buffer Operation C0
0: GRC_0 operates normally
1: GRA_0 and GRC_0 are used together for buffer
operation
3 to 1  All 1  Reserved
These bits are always read as 1, and cannot be
modified.
0 SYNC 0 R/W Timer Synchronization
0: TRDCNT_1 and TRDCNT_0 operate as independent
timer counters
1: TRDCNT_1 and TRDCNT_0 operate synchronously
TRDCNT_1 and TRDCNT_0 can be pre-set or
cleared synchronously