Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 280 of 584
REJ09B0240-0150
14.3.4 Timer RD Function Control Register (TRDFCR)
TFCR selects the settings and output levels for each operating mode.
Bit Bit Name
Initial
Value R/W Description
7 PWM3 1 R/W PWM3 Mode Select
Selects the PWM3 mode.
0: PWM3 mode is selected
1: PWM3 mode is not selected
This bit is valid when both bits CMD1 and CMD0 are
cleared to 0. When PWM3 mode is selected, TRDPMR,
TRDIORA, and TRDIORC are invalid.
6 STCLK 0 R/W External Clock Input Select
0: External clock input is disabled
1: External clock input is enabled
5 ADEG 0 R/W A/D Trigger Edge Select
The A/D converter registers should be set so that A/D
conversion is started by an external trigger.
0: The A/D trigger signal is asserted when TRDCNT_0
matches GRA_0 in complementary PWM mode
1: The A/D trigger signal is asserted when TRDCNT_1
underflows in complementary PWM mode
4 ADTRG 0 R/W External Trigger Disable
0: A/D trigger for PWM cycles is disabled in
complementary PWM mode
1: A/D trigger for PWM cycles is enabled in
complementary PWM mode
3 OLS1 0 R/W Output Level Select 1
Selects the counter-phase output levels in reset
synchronous PWM mode or complementary PWM
mode.
0: Initial output is high and the active level is low.
1: Initial output is low and the active level is high.