Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 282 of 584
REJ09B0240-0150
TRDCNT_0
Normal
phase
Counter
phase
Normal
phase
Counter
phase
Active level
Active level
Active level
Active level
Complementary PWM mode
Note: Write H'00 to TOCR to start initial outputs after stopping the counter.
Reset synchronous PWM mode
Initial
output
Initial
output
TRDCNT_1
Figure 14.7 Example of Outputs in Reset Synchronous PWM Mode
and Complementary PWM Mode
14.3.5 Timer RD Output Master Enable Register 1 (TRDOER1)
TRDOER1 enables/disables the outputs for channel 0 and channel 1. When TRDOI is selected for
inputs, if a low level signal is input to TRDOI, the bits in TRDOER1 are set to 1 to disable the
output for timer RD.
Bit Bit Name
Initial
Value R/W Description
7 ED1 1 R/W Master Enable D1
0: FTIOD1 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORC_1 settings
1: FTIOD1 pin output is disabled regardless of the
TRDMR, TRDFCR, and TRDIORC_1 settings
(FTIOD1 pin is operated as an I/O port).
6 EC1 1 R/W Master Enable C1
0: FTIOC1 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORC_1 settings
1: FTIOC1 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORC_1 settings
(FTIOC1 pin is operated as an I/O port).