Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 284 of 584
REJ09B0240-0150
14.3.6 Timer RD Output Master Enable Register 2 (TRDOER2)
TRDOER2 selects the output disabled mode for channels 0 and 1.
Bit Bit Name
Initial
Value R/W Description
7 PTO 0 R/W Timer Output Disabled Mode
0: The corresponding bit in TRDOER1 is not set to 1
when the low level is input to the TRDOI pin
1: The corresponding bit in TRDOER1 is set to 1 when
the low level is input to the TRDOI pin
6 to 0  All 1  Reserved
These bits are always read as 1.
14.3.7 Timer RD Output Control Register (TRDOCR)
TRDOCR selects the initial outputs before the first occurrence of a compare match. Note that bits
OLS1 and OLS0 in TRDFCR set these initial outputs in reset synchronous PWM mode and
complementary PWM mode.
In PWM3 mode, TRDOCR selects the output level on the FTIOB0 pin.
Bit Bit Name
Initial
Value R/W Description
7 TOD1 0 R/W Output Level Select D1
0: 0 output at the FTIOD1 pin*
1: 1 output at the FTIOD1 pin*
6 TOC1 0 R/W Output Level Select C1
0: 0 output at the FTIOC1 pin*
1: 1 output at the FTIOC1 pin*
5 TOB1 0 R/W Output Level Select B1
0: 0 output at the FTIOB1 pin*
1: 1 output at the FTIOB1 pin*