Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 286 of 584
REJ09B0240-0150
14.3.8 Timer RD Counter (TRDCNT)
Timer RD has two TRDCNT counters (TRDCNT_0 and TRDCNT_1), one for each channel. The
TRDCNT counters are 16-bit readable/writable registers that increment/decrement according to
input clocks. Input clocks can be selected by bits TPSC2 to TPSC0 in TRDCR. TRDCNT_0 and
TRDCNT_1 increment/decrement in complementary PWM mode, while they only increment in
other modes.
The TRDCNT counters are initialized to H'0000 by compare matches with corresponding GRA,
GRB, GRC, or GRD, or input captures to GRA, GRB, GRC, or GRD (counter clearing function).
When the TRDCNT counters overflow, an OVF flag in TRDSR for the corresponding channel is
set to 1. When TRDCNT_1 underflows, an UDF flag in TRDSR is set to 1. The TRDCNT
counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
TRDCNT is initialized to H'0000 by a reset.
14.3.9 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)
GR are 16-bit registers. Timer RD has eight general registers (GR), four for each channel. The GR
registers are dual function 16-bit readable/writable registers, functioning as either output compare
or input capture registers. Functions can be switched by TRDIORA and TRDIORC.
The values in GR and TRDCNT are constantly compared with each other when the GR registers
are used as output compare registers. When the both values match, the IMFA to IMFD flags in
TSR are set to 1. Compare match outputs can be selected by TRDIORA and TRDIORC.
When the GR registers are used as input capture registers, the TRDCNT value is stored after
detecting external signals. At this point, IMFA to IMFD flags in the corresponding TRDSR are set
to 1. Detection edges for input capture signals can be selected by TRDIORA and TRDIORC.
When PWM mode, complementary PWM mode, or reset synchronous PWM mode is selected, the
values in TRDIORA and TRDIORC are ignored. Upon reset, the GR registers are set as output
compare registers (no output) and initialized to H'FFFF. The GR registers cannot be accessed in 8-
bit units; they must always be accessed as a 16-bit unit.