Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 287 of 584
REJ09B0240-0150
14.3.10 Timer RD Control Register (TRDCR)
TRDCR selects a TRDCNT counter clock, an edge when an external clock is selected, and counter
clearing sources. Timer RD has a total of two TRDCR registers, one for each channel.
Bit Bit Name
Initial
Value R/W Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 2 to 0
000: Disables TRDCNT clearing
001: Clears TRDCNT by GRA compare match/input
capture*
1
010: Clears TRDCNT by GRB compare match/input
capture*
1
011: Synchronization clear; Clears TRDCNT in
synchronous with counter clearing of the other
channel's timer*
2
100: Disables TRDCNT clearing
101: Clears TRDCNT by GRC compare match/input
capture*
1
110: Clears TRDCNT by GRD compare match/input
capture*
1
111: Synchronization clear; Clears TRDCNT in
synchronous with counter clearing of the other
channel's timer*
2
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges