Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 288 of 584
REJ09B0240-0150
Bit Bit Name
Initial
Value R/W Description
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Time Prescaler 2 to 0
000: Internal clock: count by φ*
3
001: Internal clock: count by φ/2
010: Internal clock: count by φ/4
011: Internal clock: count by φ/8
100: Internal clock: count by φ/32
101: External clock: count by FTIOA0 (TCLK) pin input
110: Internal clock: count by φ40M*
4
111: Reserved (setting prohibited)
Notes: 1. When selecting the internal clock φ, the
subclock is counted in subactive and
subsleep modes.
2. When selecting the internal clock φ40M, on-
chip oscillator should be in operation. When
switching the clock, the counter should be
halted.
[Legend] X: Don't care
Notes: 1. When GR functions as an output compare register, TRDCNT is cleared by compare
match. When GR functions as input capture, TRDCNT is cleared by input capture.
2. Synchronous operation is set by TRDMDR.