Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 289 of 584
REJ09B0240-0150
14.3.11 Timer RD I/O Control Registers (TRDIORA and TRDIORC)
TRDIOR control the general registers (GR). Timer RD has four TRDIOR registers (TRDIORA_0,
TRDIORA_1, TRDIORC_0, and TRDIORC_1), two for each channel. In PWM mode, PWM3
mode, complementary PWM mode, and reset synchronous PWM mode, the settings of TRDIOR
are invalid.
• TRDIORA
TRDIORA selects whether GRA or GRB is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected.
When an input capture register is selected, an input edge of an input capture signal is selected.
TRDIORA also selects the function of FTIOA or FTIOB pin.
Bit Bit Name
Initial
Value R/W Description
7  1  Reserved
This bit is always read as 1.
6 IOB2 0 R/W I/O Control B2
Selects the GRB function.
0: GRB functions as an output compare register
1: GRB functions as an input capture register
5
4
IOB1
IOB0
0
0
R/W
R/W
I/O Control B1 and B0
When IOB2 = 0,
00: No output at compare match
01: 0 output to the FTIOB pin at GRB compare match
10: 1 output to the FTIOB pin at GRB compare match
11: Output toggles to the FTIOB pin at GRB compare
match
When IOB2 = 1,
00: Input capture to GRB at rising edge at the FTIOB
pin
01: Input capture to GRB at falling edge at the FTIOB
pin
1X: Input capture to GRB at rising and falling edges at
the FTIOB pin