Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 292 of 584
REJ09B0240-0150
Bit Bit Name
Initial
Value R/W Description
3 IOC3 1 R/W I/O Control C3
Specifies GRC to be used as GR for the FTIOA or
FTIOC pin.
0: GRC is used as GR for the FTIOA pin
1: GRC is used as GR for the FTIOC pin
2 IOC2 0 R/W I/O Control C2
Selects the GRC function.
0: GRC functions as an output compare register
1: GRC functions as an input capture register
1
0
IOC1
IOC0
0
0
R/W
R/W
I/O Control C1 and C0
When IOC3 = 0,
00: No output at compare match
01: 0 output to the FTIOA pin at GRC compare match
10: 1 output to the FTIOA pin at GRC compare match
11: Output toggles to the FTIOA pin at GRC compare
match
When IOC3 = 1 and IOC2 = 0,
00: No output at compare match
01: 0 output to the FTIOC pin at GRC compare match
10: 1 output to the FTIOC pin at GRC compare match
11: Output toggles to the FTIOC pin at GRC compare
match
When IOC3 = 1 and IOC2 = 1,
00: Input capture to GRC at rising edge at the FTIOC
pin
01: Input capture to GRC at falling edge at the FTIOC
pin
1X: Input capture to GRC at rising and falling edges at
the FTIOC pin
[Legend]
X: Don't care.
Note: When a GR register functions as a buffer register for a paired GR register, the settings in
the IOA2 and IOB2 bits in TRDIORA and the IOC2 and IOD2 bits in TRDIORC of both
registers should be the same.