Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 293 of 584
REJ09B0240-0150
14.3.12 Timer RD Status Register (TRDSR)
TRDSR indicates generation of an overflow/underflow of TRDCNT and a compare match/input
capture of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is
enabled by a corresponding bit in TRDIER, TRDSR requests an interrupt for the CPU. Timer RD
has two TRDSR registers, one for each channel.
Bit Bit Name
Initial
Value R/W Description
7, 6  All 1  Reserved
These bits are always read as 1.
5 UDF* 0 R/W Underflow Flag
[Setting condition]
• When TRDCNT_1 underflows
[Clearing condition]
• When 0 is written to UDF after reading UDF = 1
4 OVF 0 R/W Overflow Flag
[Setting condition]
• When the TRDCNT value underflows
[Clearing condition]
• When 0 is written to OVF after reading OVF = 1
3 IMFD 0 R/W Input Capture/Compare Match Flag D
[Setting conditions]
• When TRDCNT = GRD and GRD is functioning as
output compare register
• When TRDCNT = GRD while the FTIOD pin
operates in PWM mode
• When TRDCNT = GRD in PWM3 mode, reset
synchronous PWM mode, or complementary PWM
mode
• When TRDCNT value is transferred to GRD by input
capture signal and GRD is functioning as input
capture register
[Clearing condition]
• When 0 is written to IMFD after reading IMFD = 1