Datasheet

Rev. 1.50 Sep. 18, 2007 Page xxxi of xxxiv
Tables
Section 1 Overview
Table 1.1
Pin Functions ............................................................................................................ 6
Section 2 CPU
Table 2.1 Operation Notation ................................................................................................. 20
Table 2.2 Data Transfer Instructions.......................................................................................21
Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 22
Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 23
Table 2.4 Logic Operations Instructions.................................................................................24
Table 2.5 Shift Instructions..................................................................................................... 24
Table 2.6 Bit Manipulation Instructions (1)............................................................................ 25
Table 2.6 Bit Manipulation Instructions (2)............................................................................ 26
Table 2.7 Branch Instructions ................................................................................................. 27
Table 2.8 System Control Instructions.................................................................................... 28
Table 2.9 Block Data Transfer Instructions ............................................................................ 29
Table 2.10 Addressing Modes .................................................................................................. 31
Table 2.11 Absolute Address Access Ranges ........................................................................... 32
Table 2.12 Effective Address Calculation (1)........................................................................... 34
Table 2.12 Effective Address Calculation (2)........................................................................... 35
Section 3 Exception Handling
Table 3.1 Exception Sources and Vector Address.................................................................. 46
Table 3.2 Interrupt request and ICR........................................................................................55
Table 3.3 Interrupt Wait States ............................................................................................... 62
Section 4 Address Break
Table 4.1 Access and Data Bus Used .....................................................................................67
Section 5 Clock Pulse Generators
Table 5.1 Crystal Resonator Parameters .................................................................................85
Section 6 Power-Down Modes
Table 6.1 Operating Frequency and Waiting Time................................................................. 92
Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due
to Interrupt .............................................................................................................. 98
Table 6.3 Internal State in Each Operating Mode................................................................... 99
Section 7 ROM
Table 7.1 Setting Programming Modes ................................................................................ 111
Table 7.2 Boot Mode Operation ........................................................................................... 113