Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 294 of 584
REJ09B0240-0150
Bit Bit Name
Initial
Value R/W Description
2 IMFC 0 R/W Input Capture/Compare Match Flag C
[Setting conditions]
• When TRDCNT = GRC and GRC is functioning as
output compare register
• When TRDCNT = GRC while the FTIOC pin
operates in PWM mode
• When TRDCNT = GRC in PWM3 mode, reset
synchronous PWM mode, or complementary PWM
mode
• When TRDCNT value is transferred to GRC by input
capture signal and GRC is functioning as input
capture register
[Clearing condition]
• When 0 is written to IMFC after reading IMFC = 1
1 IMFB 0 R/W Input Capture/Compare Match Flag B
[Setting conditions]
• When TRDCNT = GRB and GRB is functioning as
output compare register
• When TRDCNT = GRB while the FTIOB pin
operates in PWM mode
• When TRDCNT = GRB in PWM mode, PWM3
mode, reset synchronous PWM mode, or
complementary PWM mode (in reset synchronous
PWM mode, however, while TRDCNT_0 = GRB_1
and TRDCNT_0 = GRB_0)
• When TRDCNT value is transferred to GRB by input
capture signal and GRB is functioning as input
capture register
[Clearing condition]
• When 0 is written to IMFB after reading IMFB = 1