Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 295 of 584
REJ09B0240-0150
Bit Bit Name
Initial
Value R/W Description
0 IMFA 0 R/W Input Capture/Compare Match Flag A
[Setting conditions]
• When TRDCNT = GRA and GRA is functioning as
output compare register
• When TRDCNT = GRA in PWM mode, PWM3
mode, reset synchronous PWM mode, or
complementary PWM mode (in reset synchronous
PWM mode, however, while TRDCNT_0 = GRA_1
and TRDCNT_0 = GRA_0)
• When TRDCNT value is transferred to GRA by input
capture signal and GRA is functioning as input
capture register
[Clearing condition]
• When 0 is written to IMFA after reading IMFA = 1
Note: Bit 5 is not the UDF flag in TRDSR_0. It is a reserved bit. It is always read as 1.