Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 298 of 584
REJ09B0240-0150
14.3.15 Timer RD Digital Filtering Function Select Register (TRDDF)
TRDDF enables or disables the digital filter for each of the FTIOA to FTIOD pins. The setting in
this register is valid on the corresponding pin when the FTIOA to FTIOD inputs are enabled by
TRDIORA and TRDIORC.
Timer RD has two TRDDF registers, one for each channel.
Bit Bit Name
Initial
Value R/W Description
7
6
DFCK1
DFCK0
0
0
R/W
R/W
These bits select the clock to be used by the digital
filter.
00: φ/32
01: φ/8
10: φ
11: Clock specified by bits TPSC2 to TPSC0 in TRDCR
5
4
—
—
0
0
—
—
Reserved
These bits are always read as 0.
3 DFD 0 R/W Enables or disables the digital filter for the FTIOD pin.
0: Disables the digital filter
1: Enables the digital filter
2 DFC 0 R/W Enables or disables the digital filter for the FTIOC pin.
0: Disables the digital filter
1: Enables the digital filter
1 DFB 0 R/W Enables or disables the digital filter for the FTIOB pin.
0: Disables the digital filter
1: Enables the digital filter
0 DFA 0 R/W Enables or disables the digital filter for the FTIOA pin.
0: Disables the digital filter
1: Enables the digital filter