Datasheet

Section 14 Timer RD

Rev. 1.50 Sep. 18, 2007 Page 300 of 584

REJ09B0240-0150

14.4 Operation

Timer RD has the following operating modes.

• Timer mode operation

 Enables output compare and input capture functions by setting the IOA2 to IOA0 and IOB2

to IOB0 bits in TRDIORA and the IOC3 to IOC0 and IOD3 to IOD0 bits in TRDIORC

• PWM mode operation

 Enables PWM mode operation by setting TRDPMR

• PWM3 mode operation

 Enables PWM3 mode operation by setting the PWM3 bit in TRDFCR

• Reset synchronous PWM mode operation

 Enables reset synchronous PWM mode operation by setting the CMD1 and CMD0 bits in

TRDFCR

• Complementary PWM mode operation

 Enables complementary PWM mode operation by setting the CMD1 and CMD0 bits in

TRDFCR

The FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pins indicate the timer operation mode by each

• FTIOA0 pin

Name TRDOER1 TRCMR TRDIORA

Bit Name EA0 STCLK

CMD1,

CMD0 PWM3

IOA2 to

IOA0 Function

0 0 00 0 XXX PWM3 mode waveform output

0 0 00 1 001, 01X Timer mode waveform output

(output compare function)

1 XX 1 1XX Timer mode (input capture

function)

Setting

values

Other than above General I/O port

[Legend]

X: Don't care.