Datasheet

Rev. 1.50 Sep. 18, 2007 Page xxxii of xxxiv
Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate
is Possible ............................................................................................................. 114
Table 7.4 Reprogramming Data Computation Table............................................................ 117
Table 7.5 Additional-Program Data Computation Table...................................................... 117
Table 7.6 Programming Time............................................................................................... 117
Table 7.7 Flash Memory Operating States............................................................................ 122
Section 10 Realtime Clock (RTC)
Table 10.1 Pin Configuration.................................................................................................. 188
Table 10.2 Interrupt Sources................................................................................................... 197
Section 11 Timer B1
Table 11.1 Pin Configuration.................................................................................................. 199
Table 11.2 Timer B1 Operating Modes .................................................................................. 202
Section 12 Timer V
Table 12.1 Pin Configuration.................................................................................................. 204
Table 12.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 207
Section 13 Timer RC
Table 13.1 Timer RC Functions ............................................................................................. 218
Table 13.2 Pin Configuration.................................................................................................. 220
Table 13.3 Pin Configuration in PWM2 Mode and GR Registers.......................................... 247
Section 14 Timer RD
Table 14.1 Timer RD Functions ............................................................................................. 267
Table 14.2 Channel Configuration of Timer RD .................................................................... 268
Table 14.3 Pin Configuration.................................................................................................. 272
Table 14.4 Initial Output Level of FTIOB0 Pin...................................................................... 317
Table 14.5 Output Pins in Reset Synchronous PWM Mode................................................... 322
Table 14.6 Register Settings in Reset Synchronous PWM Mode........................................... 322
Table 14.7 Output Pins in Complementary PWM Mode........................................................ 326
Table 14.8 Register Settings in Complementary PWM Mode................................................ 326
Table 14.9 Pin Configuration in PWM3 Mode and GR Registers.......................................... 333
Table 14.10 Register Combinations in Buffer Operation ..................................................... 336
Section 16 14-Bit PWM
Table 16.1 Pin Configuration.................................................................................................. 365
Section 17 Serial Communication Interface 3 (SCI3)
Table 17.1 Channel Configuration.......................................................................................... 370
Table 17.2 Pin Configuration.................................................................................................. 372
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 380
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 381