Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 306 of 584
REJ09B0240-0150
14.4.1 Counter Operation
When one of bits STR0 and STR1 in TRDSTR is set to 1, the TRDCNT counter for the
corresponding channel begins counting. TRDCNT can operate as a free-running counter, periodic
counter, for example. Figure 14.10 shows an example of the counter operation setting procedure.
[1] Select the counter clock with bits
TPSC2 to TPSC0 in TRDCR. When
an external clock is selected, select
the external clock edge with bits
CKEG1 and CKEG0 in TRDCR.
[2] For periodic counter operation, select
the TRDCNT clearing source with bits
CCLR2 to CCLR0 in TRDCR.
[3] Designate the general register
selected in [2] as an output ompare
register by means of TRDIOR.
[4] Set the periodic counter cycle in the
general register selected in [2].
[5] Set the STR bit in TRDSTR to 1 to
start the counter operation.
Operation selection
[1]
Select counter clock
[2]
Select counter clearing source
[3]
Select output compare register
[5]
Start count operation
[4]
Set period
Periodic counter Free-running counter
Figure 14.10 Example of Counter Operation Setting Procedure