Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 309 of 584
REJ09B0240-0150
• External clock operation
An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TRDCR, and
a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the
rising edge, falling edge, or both edges can be selected.
Figure 14.14 illustrates the detection timing of the rising and falling edges.
TRDCNT
External clock
input pin
TRDCNT input
N-1 N N+1
φ
Figure 14.14 Count Timing at External Clock Operation (Both Edges Detected)
14.4.2 Waveform Output by Compare Match
Timer RD can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or
FTIOD output pin using compare match A, B, C, or D.
Figure 14.15 shows an example of the setting procedure for waveform output by compare match.
[1] Select 0 output, 1 output, or toggle
output as a compare much output, by
means of TRDIOR. The initial values set
in TRDOCR are output unit the first
compare match occurs.
[2] Set the timing for compare match
generation in GRA/GRB/GRC/GRD.
[3] Enable or disable the timer output by
TRDOER1.
[4] Set the STR bit in TRDSTR to 1 to start
the TRDCNT count operation.
[1]
Output selection
Select waveform output mode
[2]
Set output timing
[3]
Enable waveform output
[4]
Start count operation
<Waveform output>
Figure 14.15 Example of Setting Procedure for Waveform Output by Compare Match