Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 311 of 584
REJ09B0240-0150
GRB
GRA
H'0000
FTIOB
Toggle output
Toggle output
Time
TRDCNT value
FTIOA
Figure 14.17 Example of Toggle Output Operation
(2) Output Compare Timing
The compare match signal is generated in the last state in which TRDCNT and GR match (when
TRDCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TRDIOR is output at the compare match output pin
(FTIOA, FTIOB, FTIOC, or FTIOD). When TRDCNT matches GR, the compare match signal is
generated only after the next TRDCNT input clock pulse is input.
Figure 14.18 shows an example of the output compare timing.
TRDCNT input
φ
Compare match
signal
TRDCNT
GR
N
N
N+1
FTIOA to FTIOD
Figure 14.18 Output Compare Timing