Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 320 of 584
REJ09B0240-0150
Figures 14.27 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 14.28 (when
TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1) show examples of the output of PWM
waveforms with duty cycles of 0% and 100% in PWM mode.
GRA
TRDCNT value
0% duty
0% duty
Time
Time
Time
GRB rewritten
TRDCNT value
GRB rewritten
GRB
rewritten
GRB rewritten
TRDCNT value
GRB rewritten
GRB rewritten
GRB rewritten
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
When cycle register and duty register compare matches
occur simultaneously, duty register compare match has
priority.
GRB rewritten
100% duty
100% duty
GRB
H'0000
FTIOB
GRA
GRB
H'0000
FTIOB
GRA
GRB
H'0000
FTIOB
Figure 14.27 Example of PWM Mode Operation (3)