Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 325 of 584
REJ09B0240-0150
GRA_0
GRB_0
GRA_1
GRB_1
H'0000
FTIOA1
FTIOB1
FTIOB0
FTIOC1
FTIOD1
FTIOC0
FTIOD0
TRDCNT value
Counter cleared by GRA compare match
Time
Figure 14.31 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0)
In reset synchronous PWM mode, TRDCNT_0 and TRDCNT_1 perform increment and
independent operations, respectively. However, GRA_1 and GRB_1 are separated from
TRDCNT_1. When a compare match occurs between TRDCNT_0 and GRA_0, a counter is
cleared and an increment operation is restarted from H'0000.
The PWM pin outputs 0 or 1 whenever a compare match between GRB_0, GRA_1, GRB_1 and
TRDCNT_0 or counter clearing occur.
For details on operations when reset synchronous PWM mode and buffer operation are
simultaneously set, refer to section 14.4.9, Buffer Operation.