Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 335 of 584
REJ09B0240-0150
Figure 14.40 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0.
In this example, TRDCNT_0 functions as a periodic counter which is cleared on compare match
A0 (bits CCLR2 to CCLR0 in TRDCR_0 are set to B'001), and PWM3 mode is selected (bit
PWM3 in TRDFCR is cleared to 0). The cycle of the pulse is arbitrary.
TRDCNT value
H'FFFF
H'0000
GRA_0
GRA_1
GRB_0
GRB_1
FTIOA0
FTIOB0
Counter cleared on GRA_0
compare match
Time
Figure 14.40 Example of Non-Overlap Pulses