Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 336 of 584
REJ09B0240-0150
14.4.9 Buffer Operation
Buffer operation differs depending on whether GR has been designated for an input capture
register or an output compare register, or in reset synchronous PWM mode or complementary
PWM mode.
Table 14.10 shows the register combinations used in buffer operation.
Table 14.10 Register Combinations in Buffer Operation
General Register (GR) Buffer Register
GRA GRC
GRB GRD
(1) When GR is an Output Compare Register
When a compare match occurs, the value in GR of the corresponding channel is transferred to the
general register.
This operation is illustrated in figure 14.41.
Buffer register Comparator TRDCNT
General
register
Compare match signal
Figure 14.41 Compare Match Buffer Operation