Datasheet

Section 14 Timer RD

Rev. 1.50 Sep. 18, 2007 Page 339 of 584

REJ09B0240-0150

(7) Examples of Buffer Operation

Figure 14.44 shows an operation example in which GRA has been designated as an output

compare register, and buffer operation has been designated for GRA and GRC.

This is an example of TRDCNT operating as a periodic counter cleared by compare match B.

Pins FTIOA and FTIOB are set for toggle output by compare match A and B.

As buffer operation has been set, when compare match A occurs, the FTIOA pin performs toggle

outputs and the value in buffer register is simultaneously transferred to the general register. This

operation is repeated each time that compare match A occurs.

The timing to transfer data is shown in figure 14.45.

GRB

TRDCNT value

Counter is cleared by GBR compare match

Time

Compare match A

H'0250

H'0200

H'0100

H'0000

FTIOB

FTIOA

H'0200

H'0250

H'0200

H'0100

H'0200

GRC

H'0100

GRA

Figure 14.44 Example of Buffer Operation (1)

(Buffer Operation for Output Compare Register)