Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 340 of 584
REJ09B0240-0150
GRA Nn
TRDCNT
Compare match
signal
Buffer transfer
signal
n
n+1
GRC
N
φ
Figure 14.45 Example of Compare Match Timing for Buffer Operation
Figure 14.46 shows an operation example in which GRA has been designated as an input capture
register, and buffer operation has been designated for GRA and GRC.
Counter clearing by input capture B has been set for TRDCNT, and falling edges have been
selected as the FIOCB pin input capture input edge. And both rising and falling edges have been
selected as the FIOCA pin input capture input edge.
As buffer operation has been set, when the TRDCNT value is stored in GRA upon the occurrence
of input capture A, the value previously stored in GRA is simultaneously transferred to GRC. The
transfer timing is shown in figure 14.47.