Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 344 of 584
REJ09B0240-0150
14.4.10 Timer RD Output Timing
The outputs of channels 0 and 1 can be disabled or inverted by the settings of TRDOER1 and
TRDOCR and the external level.
(1) Output Disable/Enable Timing of Timer RD by TRDOER1
Setting the master enable bit in TRDOER1 to 1 disables the output of timer RD. By setting the
PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 14.50
shows the timing to enable or disable the output of timer RD by TRDOER1.
T
1
T
2
TRDOER1
Address bus
TRDOER1 address
Timer RD
output pin
Timer RD output
I/O port
I/O port
Timer output
φ
T
3
T
4
0
1
Figure 14.50 Example of Output Disable Timing of Timer RD by Writing to TRDOER1
(2) Output Disable Timing of Timer RD by External Trigger
When PH5/TRDOI_0 (or PH6/TRDOI_1) is set as a TRDOI input pin, and low level is input to
TRDOI, the master enable bit in TRDOER1 is set to 1 and the output of timer RD will be disabled.
TRDOI
TRDOER1
Timer RD
output pin
Timer RD output
I/O port
Timer RD output
I/O port
0
1
φ
Figure 14.51 Example of Output Disable Timing of Timer RD by External Trigger