Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 345 of 584
REJ09B0240-0150
(3) Output Inverse Timing by TRDFCR
The output level can be inverted by inverting the OLS1 and OLS0 bits in TRDFCR in reset
synchronous PWM mode or complementary PWM mode. Figure 14.52 shows the timing.
T 1 T 2
TRDFCR
Inverted
Timer RD
output pin
Address bus
TRDOER1 address
φ
T
3 T 4
Figure 14.52 Example of Output Inverse Timing of Timer RD by Writing to TRDFCR
(4) Output Inverse Timing by POCR
The output level can be inverted by inverting the POLD, POLC, and POLB bits in POCR in PWM
mode. Figure 14.53 shows the timing.
T 1 T 2
TRDFCR
Address bus
POCR address
Timer RD
output pin
Inverted
φ
T
3 T 4
Figure 14.53 Example of Output Inverse Timing of Timer RD by Writing to POCR