Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 346 of 584
REJ09B0240-0150
14.4.11 Digital Filtering Function for Input Capture Inputs
Input signals on the FTIOA to FTIOD pins can be input via the digital filters. The digital filter
includes three latches connected in series and a matching detecting circuit. The latches operate on
the sampling clock specified by bits DFCK1 and DFCK0 in TRDDF and stores an input signal on
the FTIOA to FTIOD pins. When outputs of the three latches match, the matching detecting circuit
outputs the signal level of the input. Otherwise, the output remains unchanged. That is, when a
pulse width is equal to or greater than three sampling clock cycles, the pulse is input as a signal.
When a pulse width is less than three sampling clock cycles, the pulse is considered as a noise to
be removed.
FTIOA0 (TCLK)
φ40M
φ/32
φ/
8
φ/
4
φ/
2
φ
FTIOA to FTIOD
input signals
Cycle of a clock specified by
TPSC2 to TPSC0 or DFCK1
and DFCK0
Signal change is not output unless
signal levels match three times.
Signal propagation delay:
5 sampling clocks
TPSC2 to
TPSC0
DFCK1 and
DFCK2
DFA to DFD
IOA1, IOA0,
IOD1, and IOD0
Sampling clock
φ/32
φ/8
φ
Matching
detecting
circuit
Selecter
Edge
detecting
circuit
Sampling clock
C
Latch
DQ
C
Latch
DQ
C
Latch
D
Q
Digital-filtered signal
φ, φ40M
C
Latch
Q
C
Latch
Q
D
D
FTIOA to FTIOD
Figure 14.54 Block Diagram of Digital Filter