Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 349 of 584
REJ09B0240-0150
14.5 Interrupt Sources
There are three kinds of timer RD interrupt sources; input capture/compare match, overflow, and
underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while
the corresponding interrupt enable bit is set to 1.
14.5.1 Status Flag Set Timing
(1) IMF Flag Set Timing
The IMF flag is set to 1 by the compare match signal that is generated when the GR matches with
the TRDCNT. The compare match signal is generated at the last state of matching (timing to
update the counter value when the GR and TRDCNT match). Therefore, when the TRDCNT and
GR matches, the compare match signal will not be generated until the TRDCNT input clock is
generated. Figure 14.58 shows the timing to set the IMF flag.
φ
TRDCNT input clock
Compare match
signal
IMF
ITMRD
TRDCNT N
N+1
GR
N
Figure 14.58 IMF Flag Set Timing when Compare Match Occurs