Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 351 of 584
REJ09B0240-0150
14.5.2 Status Flag Clearing Timing
The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 14.61 shows the
timing in this case.
φ
IMF, OVF
WTRDSR
ITMRD
Address
(internal write signal)
TRDSR address
Figure 14.61 Status Flag Clearing Timing
14.6 Usage Notes
(1) Input Pulse Width of Input Clock Signal and Input Capture Signal
The pulse width of the input clock signal and the input capture signal must be at least three system
clock (φ) cycles when bits TPSC2 to TPSC0 in TRDCR = B'0XX or B'10X, or at least three on-
chip oscillator clock (φ40M) cycles when B'110; shorter pulses will not be detected correctly.