Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 352 of 584
REJ09B0240-0150
(2) Conflict between TRDCNT Write and Clear Operations
If a counter clear signal is generated in the T
4
state of a TRDCNT write cycle, TRDCNT clearing
has priority and the TRDCNT write is not performed. Figure 14.62 shows the timing in this case.
T
1
T
2
TRDCNT
TRDCNT write cycle
TRDCNT addressAddress bus
WTRDCNT
(internal write signal)
Clearing has priority.
Counter clear signal
N
H'0000
φ
T
3
T
4
Figure 14.62 Conflict between TRDCNT Write and Clear Operations
(3) Conflict between TRDCNT Write and Increment Operations
If TRDCNT is incremented in the T
4
state of a TRDCNT write cycle, writing has priority. Figure
14.63 shows the timing in this case.
T
1
T
2
TRDCNT
TRDCNT write cycle
TRDCNT address
Address bus
WTRDCNT
(internal write signal)
TRDCNT input clock
TRDCNT write data
N
M
φ
T
3
T
4
Figure 14.63 Conflict between TRDCNT Write and Increment Operations