Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 353 of 584
REJ09B0240-0150
(4) Conflict between GR Write and Compare Match
If a compare match occurs in the T
4
state of a GR write cycle, GR write has priority and the
compare match signal is disabled. Figure 14.64 shows the timing in this case.
T
1
T
2
GR N M
TRDCNT
GR write cycle
GR addressAddress bus
WTRDCNT
(internal write signal)
GR write data
Compare match
signal
Disabled
N N+1
φ
T
3
T
4
Figure 14.64 Conflict between GR Write and Compare Match