Datasheet

Section 1 Overview
Rev. 1.50 Sep. 18, 2007 Page 3 of 584
REJ09B0240-0150
1.2 Internal Block Diagram
Port 8Port CPor DPort EPort H Port 7
Port 1Port 2Port 3Port 5
P17/IRQ3/TRGV
P16/IRQ2
P15/IRQ1/TMIB1
P14/IRQ0
P12
P11/PWM
P10/TMOW
P57/SCL
P56/SDA
P55/WKP5
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
PJ0/OSC1
PJ1/OSC2/CLKOUT
PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0
VCL V
CC
V
CC
V
SS
V
SS
V
SS
RES TEST NMI
AV
CC
AV
SS
(OSC1) (OSC2) X1 X2
CPU
H8/300H
RAM
Data bus (lower)
Data bus (upper)
14-bit PWM
Timer RD_1
Timer RD_0
SCI3
IIC2
SCI3_2
Timer V
Watchdog
timer
SCI3_3
P87
P86
P85
PD7/FTIOD1
PD6/FTIOC1
PD5/FTIOB1
PD4/FTIOA1
PD3/FTIOD0
PD2/FTIOC0
PD1/FTIOB0
PD0/FTIOA0
PE7/FTIOD3
PE6/FTIOC3
PE5/FTIOB3
PE4/FTIOA3
PE3/FTIOD2
PE2/FTIOC2
PE1/FTIOB2
PE0/FTIOA2
PH7/FTIOD
PH6/FTIOC
PH5/FTIOB
PH4/FTIOA/TRGC
PH3/FTCI
PH2/TXD_3
PH1/RXD_3
PH0/SCK3_3/ADTR
G
P37
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
P22/TXD
P21/RXD
P20/SCK3
Subclock
generator
On-chip
oscillator
System
clock
generator
Port F
Port J
PG7/AN15/TRDOI_1 PG6/AN14/TRDOI_0
PG5/AN13/TRCOI
PG4/AN12 PG3/AN11 PG2/AN10
PG1/AN9 PG0/AN8
Port G
Timer RC
Timer B1
POR and LVD
(optional)
PC3
PC2
PC1
PC0
P77
P76/TMOV
P75/TMCIV
P74/TMRIV
P72/TXD_2
P71/RXD_2
P70/SCK3_2
Address bus
ROM
RTC
A/D
Converter
Figure 1.1 Internal Block Diagram