Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 354 of 584
REJ09B0240-0150
(5) Conflict between TRDCNT Write and Overflow/Underflow
If overflow/underflow occurs in the T
4
state of a TRDCNT write cycle, TRDCNT write has
priority without an increment operation. At this time, the OVF flag is set to 1. Figure 14.65 shows
the timing in this case.
T
1
T
2
TRDCNT
H'FFFF
M
OVF
TRDCNT addressAddress bus
WTRDCNT
(internal write signal)
TRDCNT input clock
Overflow signal
TRDCNT write data
TRDCNT write cycle
φ
T
3
T
4
Figure 14.65 Conflict between TRDCNT Write and Overflow