Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 355 of 584
REJ09B0240-0150
(6) Conflict between GR Read and Input Capture
If an input capture signal is generated in the T
4
state of a GR read cycle, the data that is read will
be transferred before input capture transfer. Figure 14.66 shows the timing in this case.
T
1
T
2
GR
GR read cycle
GR addressAddress bus
Internal read
signal
Input capture
signal
Internal data
bus
X
X
M
φ
T
3
T
4
Figure 14.66 Conflict between GR Read and Input Capture
(7) Conflict between Count Clearing and Increment Operations by Input Capture
If an input capture and increment signals are simultaneously generated, count clearing by the input
capture operation has priority without an increment operation. The TRDCNT contents before
clearing counter are transferred to GR. Figure 14.67 shows the timing in this case.
TRDCNT
Input capture
signal
Counter clear
signal
TRDCNT input
clock
Clearing has priority.
N
H'0000
GR
N
φ
Figure 14.67 Conflict between Count Clearing and Increment Operations
by Input Capture