Datasheet

Section 14 Timer RD
Rev. 1.50 Sep. 18, 2007 Page 356 of 584
REJ09B0240-0150
(8) Conflict between GR Write and Input Capture
If an input capture signal is generated in the T
4
state of a GR write cycle, the input capture
operation has priority and the write to GR is not performed. Figure 14.68 shows the timing in this
case.
T
1
T
2
TRDCNT
N
GR write cycle
GR address
Input capture
signal
WGR
(internal write signal)
Address bus
GR write data
GR
M
φ
T
3
T
4
Figure 14.68 Conflict between GR Write and Input Capture
(9) Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode
When bits CMD1 and CMD0 in TRDFCR are set, note the following:
• Write bits CMD1 and CMD0 while TRDCNT_1 and TRDCNT_0 are halted.
• Changing the settings of reset synchronous PWM mode to complementary PWM mode or vice
versa is disabled. Set reset synchronous PWM mode or complementary PWM mode after the
normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.